The invention relates to traffic analyzer, and particularly, to traffic analyzer and accordingly power state management in bridge logic.
Power management has become a significant issue in computer design. Central processing units (CPUs) and main memories (random access memories, RAMs) typically consume more power than other units in a computer system as they operate at high clocking frequency. Therefore, CPUs and main memory both play a critical role in reducing computer system power consumption and performance efficiency.
The Advanced Configuration and Power Interface (ACPI) specification provides several methods of controlling processor performance states via operating system-directed configuration and power management (OSPM), by which CPUs may be transited to performance states of high operating voltage and frequency when busy. Managing CPU performance states by an OS, however, may be a heavy load for a busy CPU and may thus reduce CPU efficiency.
Additionally, desired power saving may be improved by aggressive power management, which is typically performed by an OS. Frequent activities caused by aggressive power management, however, may adversely affect CPU performance.
As is well known in the art, the clock frequency of random access memory (RAM) can be configured via the basic input/output system (BIOS) before a system boot. Despite the run-time variation of main memory access workload, a main memory operates at a configured clock frequency until the system shuts down. Infrequently serving access activities at high main memory operating frequency consumes excessive power, while frequently serving access activities at low main memory operating frequency is inefficient.